Struct daisy::pac::sdmmc1::maskr::W

pub struct W(/* private fields */);

Register MASKR writer

Implementations

impl W

pub fn ccrcfailie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 0>

Bit 0 - Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure.

pub fn dcrcfailie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 1>

Bit 1 - Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure.

pub fn ctimeoutie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 2>

Bit 2 - Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout.

pub fn dtimeoutie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 3>

Bit 3 - Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout.

pub fn txunderrie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 4>

Bit 4 - Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.

pub fn rxoverrie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 5>

Bit 5 - Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.

pub fn cmdrendie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 6>

Bit 6 - Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response.

pub fn cmdsentie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 7>

Bit 7 - Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.

pub fn dataendie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 8>

Bit 8 - Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end.

pub fn dholdie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 9>

Bit 9 - Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state.

pub fn dbckendie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 10>

Bit 10 - Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end.

pub fn dabortie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 11>

Bit 11 - Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted.

pub fn txfifoheie( &mut self ) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 14>

Bit 14 - Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.

pub fn rxfifohfie( &mut self ) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 15>

Bit 15 - Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.

pub fn rxfifofie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 17>

Bit 17 - Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.

pub fn txfifoeie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 18>

Bit 18 - Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.

pub fn busyd0endie( &mut self ) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 21>

Bit 21 - BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response.

pub fn sdioitie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 22>

Bit 22 - SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt.

pub fn ackfailie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 23>

Bit 23 - Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.

pub fn acktimeoutie( &mut self ) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 24>

Bit 24 - Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.

pub fn vswendie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 25>

Bit 25 - Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion.

pub fn ckstopie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 26>

Bit 26 - Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped.

pub fn idmabtcie(&mut self) -> BitWriterRaw<'_, u32, MASKR_SPEC, bool, BitM, 28>

Bit 28 - IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<MASKR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<MASKR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<MASKR_SPEC>> for W

fn from(writer: W<MASKR_SPEC>) -> W

Converts to this type from the input type.