Struct daisy::pac::rcc::cr::W

pub struct W(/* private fields */);

Register CR writer

Implementations

impl W

pub fn hsion(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 0>

Bit 0 - Internal high-speed clock enable

pub fn hsikeron(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 1>

Bit 1 - High Speed Internal clock enable in Stop mode

pub fn hsirdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 2>

Bit 2 - HSI clock ready flag

pub fn hsidiv( &mut self ) -> FieldWriterRaw<'_, u32, CR_SPEC, u8, HSIDIV_A, Safe, 2, 3>

Bits 3:4 - HSI clock divider

pub fn hsidivf(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIDIVF_A, BitM, 5>

Bit 5 - HSI divider flag

pub fn csion(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 7>

Bit 7 - CSI clock enable

pub fn csirdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 8>

Bit 8 - CSI clock ready flag

pub fn csikeron(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 9>

Bit 9 - CSI clock enable in Stop mode

pub fn hsi48on(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 12>

Bit 12 - RC48 clock enable

pub fn hsi48rdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 13>

Bit 13 - RC48 clock ready flag

pub fn d1ckrdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 14>

Bit 14 - D1 domain clocks ready flag

pub fn d2ckrdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 15>

Bit 15 - D2 domain clocks ready flag

pub fn hseon(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 16>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 17>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSEBYP_A, BitM, 18>

Bit 18 - HSE clock bypass

pub fn hsecsson(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 19>

Bit 19 - HSE Clock Security System enable

pub fn pll1on(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 24>

Bit 24 - PLL1 enable

pub fn pll1rdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 25>

Bit 25 - PLL1 clock ready flag

pub fn pll2on(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 26>

Bit 26 - PLL2 enable

pub fn pll2rdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 27>

Bit 27 - PLL2 clock ready flag

pub fn pll3on(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSION_A, BitM, 28>

Bit 28 - PLL3 enable

pub fn pll3rdy(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, HSIRDY_A, BitM, 29>

Bit 29 - PLL3 clock ready flag

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CR_SPEC>> for W

fn from(writer: W<CR_SPEC>) -> W

Converts to this type from the input type.