pub struct W(/* private fields */);
Expand description
Register DCR
writer
Implementations§
§impl W
impl W
pub fn ckmode(&mut self) -> BitWriterRaw<'_, u32, DCR_SPEC, bool, BitM, 0>
pub fn ckmode(&mut self) -> BitWriterRaw<'_, u32, DCR_SPEC, bool, BitM, 0>
Bit 0 - indicates the level that clk takes between command
pub fn csht(
&mut self
) -> FieldWriterRaw<'_, u32, DCR_SPEC, u8, u8, Unsafe, 3, 8>
pub fn csht( &mut self ) -> FieldWriterRaw<'_, u32, DCR_SPEC, u8, u8, Unsafe, 3, 8>
Bits 8:10 - Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. … This field can be modified only when BUSY = 0.
pub fn fsize(
&mut self
) -> FieldWriterRaw<'_, u32, DCR_SPEC, u8, u8, Unsafe, 5, 16>
pub fn fsize( &mut self ) -> FieldWriterRaw<'_, u32, DCR_SPEC, u8, u8, Unsafe, 5, 16>
Bits 16:20 - Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0.
Methods from Deref<Target = W<DCR_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.