Struct daisy::pac::bdma::isr::R

pub struct R(/* private fields */);

Register ISR reader

Implementations

impl R

pub fn gif1(&self) -> BitReaderRaw<GIF1_A>

Bit 0 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif1(&self) -> BitReaderRaw<TCIF1_A>

Bit 1 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif1(&self) -> BitReaderRaw<HTIF1_A>

Bit 2 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif1(&self) -> BitReaderRaw<TEIF1_A>

Bit 3 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif2(&self) -> BitReaderRaw<GIF1_A>

Bit 4 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif2(&self) -> BitReaderRaw<TCIF1_A>

Bit 5 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif2(&self) -> BitReaderRaw<HTIF1_A>

Bit 6 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif2(&self) -> BitReaderRaw<TEIF1_A>

Bit 7 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif3(&self) -> BitReaderRaw<GIF1_A>

Bit 8 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif3(&self) -> BitReaderRaw<TCIF1_A>

Bit 9 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif3(&self) -> BitReaderRaw<HTIF1_A>

Bit 10 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif3(&self) -> BitReaderRaw<TEIF1_A>

Bit 11 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif4(&self) -> BitReaderRaw<GIF1_A>

Bit 12 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif4(&self) -> BitReaderRaw<TCIF1_A>

Bit 13 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif4(&self) -> BitReaderRaw<HTIF1_A>

Bit 14 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif4(&self) -> BitReaderRaw<TEIF1_A>

Bit 15 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif5(&self) -> BitReaderRaw<GIF1_A>

Bit 16 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif5(&self) -> BitReaderRaw<TCIF1_A>

Bit 17 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif5(&self) -> BitReaderRaw<HTIF1_A>

Bit 18 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif5(&self) -> BitReaderRaw<TEIF1_A>

Bit 19 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif6(&self) -> BitReaderRaw<GIF1_A>

Bit 20 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif6(&self) -> BitReaderRaw<TCIF1_A>

Bit 21 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif6(&self) -> BitReaderRaw<HTIF1_A>

Bit 22 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif6(&self) -> BitReaderRaw<TEIF1_A>

Bit 23 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif7(&self) -> BitReaderRaw<GIF1_A>

Bit 24 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif7(&self) -> BitReaderRaw<TCIF1_A>

Bit 25 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif7(&self) -> BitReaderRaw<HTIF1_A>

Bit 26 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif7(&self) -> BitReaderRaw<TEIF1_A>

Bit 27 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn gif8(&self) -> BitReaderRaw<GIF1_A>

Bit 28 - Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn tcif8(&self) -> BitReaderRaw<TCIF1_A>

Bit 29 - Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn htif8(&self) -> BitReaderRaw<HTIF1_A>

Bit 30 - Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

pub fn teif8(&self) -> BitReaderRaw<TEIF1_A>

Bit 31 - Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

Methods from Deref<Target = R<ISR_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<ISR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<ISR_SPEC>> for R

fn from(reader: R<ISR_SPEC>) -> R

Converts to this type from the input type.