Module timeoutr
Expand description
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
Structs§
- R
- Register
TIMEOUTRreader - TIMEOUTR_
SPEC - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
- W
- Register
TIMEOUTRwriter
Enums§
- TEXTEN_
A - Extended clock timeout enable
- TIDLE_A
- Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
- TIMOUTEN_
A - Clock timeout enable
Type Aliases§
- TEXTEN_
R - Field
TEXTENreader - Extended clock timeout enable - TEXTEN_
W - Field
TEXTENwriter - Extended clock timeout enable - TIDLE_R
- Field
TIDLEreader - Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. - TIDLE_W
- Field
TIDLEwriter - Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. - TIMEOUTA_
R - Field
TIMEOUTAreader - Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. - TIMEOUTA_
W - Field
TIMEOUTAwriter - Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. - TIMEOUTB_
R - Field
TIMEOUTBreader - Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. - TIMEOUTB_
W - Field
TIMEOUTBwriter - Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. - TIMOUTEN_
R - Field
TIMOUTENreader - Clock timeout enable - TIMOUTEN_
W - Field
TIMOUTENwriter - Clock timeout enable