Module sr

DAC status register

Structs

R

Register SR reader

SR_SPEC

DAC status register

W

Register SR writer

Type Aliases

BWST1_R

Field BWST1 reader - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).

BWST2_R

Field BWST2 reader - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).

CAL_FLAG1_R

Field CAL_FLAG1 reader - DAC Channel 1 calibration offset status This bit is set and cleared by hardware

CAL_FLAG2_R

Field CAL_FLAG2 reader - DAC Channel 2 calibration offset status This bit is set and cleared by hardware

DMAUDR1_R

Field DMAUDR1 reader - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

DMAUDR1_W

Field DMAUDR1 writer - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

DMAUDR2_R

Field DMAUDR2 reader - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

DMAUDR2_W

Field DMAUDR2 writer - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).