Module cr

QUADSPI control register

Structs

CR_SPEC

QUADSPI control register

R

Register CR reader

W

Register CR writer

Type Aliases

ABORT_R

Field ABORT reader - Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit.

ABORT_W

Field ABORT writer - Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit.

APMS_R

Field APMS reader - Automatic poll mode stop This bit determines if automatic polling is stopped after a match. This bit can be modified only when BUSY = 0.

APMS_W

Field APMS writer - Automatic poll mode stop This bit determines if automatic polling is stopped after a match. This bit can be modified only when BUSY = 0.

DFM_R

Field DFM reader - Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. This bit can be modified only when BUSY = 0.

DFM_W

Field DFM writer - Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. This bit can be modified only when BUSY = 0.

DMAEN_R

Field DMAEN reader - DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set.

DMAEN_W

Field DMAEN writer - DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set.

EN_R

Field EN reader - Enable Enable the QUADSPI.

EN_W

Field EN writer - Enable Enable the QUADSPI.

FSEL_R

Field FSEL reader - Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1.

FSEL_W

Field FSEL writer - Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1.

FTHRES_R

Field FTHRES reader - FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): … In indirect read mode (FMODE = 01): … If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value.

FTHRES_W

Field FTHRES writer - FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): … In indirect read mode (FMODE = 01): … If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value.

FTIE_R

Field FTIE reader - FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.

FTIE_W

Field FTIE writer - FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.

PMM_R

Field PMM reader - Polling match mode This bit indicates which method should be used for determining a match during automatic polling mode. This bit can be modified only when BUSY = 0.

PMM_W

Field PMM writer - Polling match mode This bit indicates which method should be used for determining a match during automatic polling mode. This bit can be modified only when BUSY = 0.

PRESCALER_R

Field PRESCALER reader - clock prescaler

PRESCALER_W

Field PRESCALER writer - clock prescaler

SMIE_R

Field SMIE reader - Status match interrupt enable This bit enables the status match interrupt.

SMIE_W

Field SMIE writer - Status match interrupt enable This bit enables the status match interrupt.

SSHIFT_R

Field SSHIFT reader - Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0.

SSHIFT_W

Field SSHIFT writer - Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0.

TCEN_R

Field TCEN reader - Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. This bit can be modified only when BUSY = 0.

TCEN_W

Field TCEN writer - Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. This bit can be modified only when BUSY = 0.

TCIE_R

Field TCIE reader - Transfer complete interrupt enable This bit enables the transfer complete interrupt.

TCIE_W

Field TCIE writer - Transfer complete interrupt enable This bit enables the transfer complete interrupt.

TEIE_R

Field TEIE reader - Transfer error interrupt enable This bit enables the transfer error interrupt.

TEIE_W

Field TEIE writer - Transfer error interrupt enable This bit enables the transfer error interrupt.

TOIE_R

Field TOIE reader - TimeOut interrupt enable This bit enables the TimeOut interrupt.

TOIE_W

Field TOIE writer - TimeOut interrupt enable This bit enables the TimeOut interrupt.